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CAT24C256
256-Kb I2C CMOS Serial EEPROM
fEATuRES
n Supports Standard and fast I2C Protocol n 1.8 V to 5.5 V Supply Voltage Range n 64-byte Page Write buffer n Hardware Write Protection for entire memory n Schmitt Triggers and noise Suppression filters
DEVICE DESCRIPTIOn
The CAT24C256 is a 256-Kb Serial CMOS EEPROM, internally organized as 52 pages of 64 bytes each, for a total of 32,768 bytes of 8 bits each. It features a 64-byte page write buffer and supports both the Standard (00 kHz) as well as Fast (400 kHz) I2C protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory). External address pins make it possible to address up to eight CAT24C256 devices on the same bus.
on I2C bus Inputs (SCl and SDA).
n low power CMOS technology n 1,000,000 program/erase cycles n 100 year data retention n Industrial temperature range n RoHS-compliant 8-pin PDIP and SOIC packages
for Ordering Information details, see page 13.
PIn COnfIguRATIOn
PDIP (l) SOIC (W, X)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
funCTIOnAl SyMbOl
VCC
SCL A2, A1, A0 WP CAT24C256 SDA
For the location of Pin , please consult the corresponding package drawing.
PIn funCTIOnS
A0, A, A2 SDA SCL WP VCC VSS Device Address Serial Data Serial Clock Write Protect Power Supply Ground
VSS
* Catalyst carries the I2C protocol under a license from the Philips Corporation.
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Doc. No. 04, Rev. D
CAT24C256
AbSOluTE MAXIMuM RATIngS(1) Storage Temperature Voltage on Any Pin with Respect to Ground(2) -65C to +50C -0.5 V to +6.5 V
RElIAbIlITy CHARACTERISTICS(3) Symbol NEND
(4)
Parameter Endurance Data Retention
Min ,000,000 00
units Program/ Erase Cycles Years
TDR
D.C. OPERATIng CHARACTERISTICS VCC = .8 V to 5.5 V, TA = -40C to 85C, unless otherwise specified. Symbol ICC ISB IL VIL VIH VOL VOL2 Parameter Supply Current Standby Current I/O Pin Leakage Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage VCC > 2.5 V, IOL = 3.0 mA VCC > .8 V, IOL = .0 mA Test Conditions Read or Write at 400 kHz All I/O Pins at GND or VCC Pin at GND or VCC -0.5 Min Max VCC x 0.3 0.4 0.2 VCC x 0.7 VCC + 0.5 units mA A A V V V V
PIn IMPEDAnCE CHARACTERISTICS TA = 25C, f = 400 kHz, VCC = 5 V Symbol CIN
notes: () Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -.5 V or overshoot to no more than VCC + .5 V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q00 and JEDEC test methods. (4) Page Mode, VCC = 5 V, 25C
(3)
Parameter SDA I/O Pin Capacitance Input Capacitance (other pins)
Conditions VIN = 0 V VIN = 0 V
Min
Max 8 6
units pF pF
CIN(3)
Doc. No. 04, Rev. D
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(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C256
A.C. CHARACTERISTICS(1) VCC = .8 V to 5.5 V, TA = -40C to 85C, unless otherwise specified. 1.8 V - 5.5 V Symbol FSCL TI(2) tAA tBUF(2) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(2) tF(2) tSU:STO tDH tWR tPU(2), (3)
notes: () Test conditions according to "A.C. Test Conditions" table. (2) Tested initially and after a design or process change that affects this parameter. (3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
2.5 V - 5.5 V Min Max 400 0. 0.9 .3 0.6 .3 0.6 0.6 0 0. units kHz s s s s s s s s s 0.3 0.3 0.6 0. s s s s 5 ms ms
Parameter Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Write Cycle Time Power-up to Ready Mode
Min
Max 00 0. 3.5
4.7 4 4.7 4 4.7 0 0.25 0.3 4 0. 5
A.C. TEST COnDITIOnS Input Levels Input Rise and Fall Times Input Reference Levels Output Reference Levels Output Load 0.2 x VCC to 0.8 x VCC
50 ns
0.3 x VCC, 0.7 x VCC 0.5 x VCC Current Source: IOL = 3 mA (VCC 2.5 V); IOL = mA (VCC < 2.5 V); CL = 00 pF
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
3
Doc No. 04, Rev. D
CAT24C256
PIn DESCRIPTIOn
SCl: The Serial Clock input pin accepts the Serial Clock generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address pins accept the device address. These pins have on-chip pull-down resistors. WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. This pin has an on-chip pull-down resistor.
START The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a `wake-up' call to all receivers. Absent a START, a Slave will not respond to commands. STOP The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP starts the internal Write cycle (when following a Write command) or sends the Slave into standby mode (when following a Read command). Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8-bit serial Slave address. The first 4 bits of the Slave address are set to 00, for normal Read/Write operations (Figure 2). The next 3 bits, A2, A and A0, select one of 8 possible Slave devices. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 3). The Slave will also acknowledge the byte address and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. If the Master acknowledges the data, then the Slave continues transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by sending a STOP to the Slave. Bus timing is illustrated in Figure 4.
funCTIOnAl DESCRIPTIOn
The CAT24C256 supports the Inter-Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT24C256 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device address inputs A0, A, and A2.
I2C buS PROTOCOl
The I2C bus consists of two `wires', SCL and SDA. The two wires are connected to the VCC supply via pull-up resistors. Master and Slave devices connect to the 2wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to `transmit' a `0' and releases it to `transmit' a `'. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure ).
Doc. No. 04, Rev. D
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(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C256
figure 1. Start/Stop Timing
SCL
SDA START CONDITION STOP CONDITION
figure 2. Slave Address bits
1
0
1
0
A2
A1
A0
R/W
DEVICE ADDRESS
figure 3. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 8 9 BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACK DELAY ( tAA) ACK SETUP ( tSU:DAT)
figure 4. bus Timing
tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tDH tBUF tHD:STA tHD:DAT tSU:DAT tSU:STO tHIGH tLOW tR
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
5
Doc No. 04, Rev. D
CAT24C256
WRITE OPERATIOnS
byte Write In Byte Write mode the Master sends a START, followed by Slave address, two byte address and data to be written (Figure 5). The Slave acknowledges all 4 bytes, and the Master then follows up with a STOP, which in turn starts the internal Write operation (Figure 6). During internal Write, the Slave will not acknowledge any Read or Write request from the Master. Page Write The CAT24C256 contains 32,768 bytes of data, arranged in 52 pages of 64 bytes each. A two byte address word, following the Slave address, points to the first byte to be written. The most significant bit of the address word is `don't care', the next 9 bits identify the page and the last 6 bits identify the byte within the page. Up to 64 bytes can be written in one Write cycle (Figure 7). The internal byte address counter is automatically incremented after each data byte is loaded. If the Master transmits more than 64 data bytes, then earlier bytes will be overwritten by later bytes in a `wrap-around' fashion (within the selected page). The internal Write cycle starts immediately following the STOP. Acknowledge Polling Acknowledge polling can be used to determine if the CAT24C256 is busy writing or is ready to accept commands. Polling is implemented by interrogating the device with a `Selective Read' command (see READ OPERATIONS). The CAT24C256 will not acknowledge the Slave address, as long as internal Write is in progress. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT24C256.
Doc. No. 04, Rev. D
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(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C256
figure 5. byte Write Timing
BUS ACTIVITY: MASTER SDA LINE
S T A R T S
SLAVE ADDRESS
BYTE ADDRESS A15-A8 A7-A0
DATA
S T O P P
* = Don't Care Bit
A C K
*
A C K
A C K
A C K
figure 6. Write Cycle Timing
SCL
SDA
8th Bit Byte n
ACK tWR STOP CONDITION START CONDITION ADDRESS
figure 7. Page Write Timing
BUS ACTIVITY: MASTER SDA LINE
S T A R T S
SLAVE ADDRESS
BYTE ADDRESS A15-A8 A7-A0
DATA
DATA n
DATA n+63
S T O P P
* = Don't Care Bit
A C K
*
A C K
A C K
A C K
A C K
A C K
A C K
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
7
Doc No. 04, Rev. D
CAT24C256
READ OPERATIOnS
Immediate Address Read In standby mode, the CAT24C256 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If that `previous' byte was the last byte in memory, then the address counter will point to the st memory byte, etc. When, following a START, the CAT24C256 is presented with a Slave address containing a `' in the R/W bit position (Figure 8), it will acknowledge (ACK) in the 9th clock cycle, and will then transmit data being pointed at by the internal address counter. The Master can stop further transmission by issuing a NoACK, followed by a STOP condition. Selective Read The Read operation can also be started at an address different from the one stored in the internal address counter. The address counter can be initialized by performing a `dummy' Write operation (Figure 9). Here the START is followed by the Slave address (with the R/W bit set to `0') and the desired two byte address. Instead of following up with data, the Master then issues a 2nd START, followed by the `Immediate Address Read' sequence, as described earlier. Sequential Read If the Master acknowledges the st data byte transmitted by the CAT24C256, then the device will continue transmitting as long as each data byte is acknowledged by the Master (Figure 0). If the end of memory is reached during sequential Read, then the address counter will `wrap-around' to the beginning of memory, etc. Sequential Read works with either `Immediate Address Read' or `Selective Read', the only difference being the starting byte address.
Doc. No. 04, Rev. D
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(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C256
figure 8. Immediate Address Read Timing
S T A R T S A C K DATA N O A C K
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
S T O P P
SCL
8
9
SDA
8th Bit DATA OUT NO ACK STOP
figure 9. Selective Read Timing
S T A R T S A C K S T A R T S A C K A C K A C K N O A C K
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
BYTE ADDRESS A15-A8 A7-A0
SLAVE ADDRESS
DATA
S T O P P
*
* = Don't Care Bit
figure 10. Sequential Read Timing
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
S T O P P
A C K
A C K
A C K
A C K
N O A C K
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
9
Doc No. 04, Rev. D
CAT24C256
PACKAgE OuTlInES
8-lEAD 300 MIl WIDE PlASTIC DIP (l)
E1
D
E
A2
A
c
A1
L
e b2 b
eB
SYMBOL A A1 A2 b b2 c D E E1 e eB L
MIN 0.38 3.05 0.36 1.14 0.21 9.02 7.62 6.09 7.87 2.92
NOM
MAX 4.57 3.81 0.56 1.77 0.35 10.16 8.25 7.11 9.65 3.81
0.46 0.26 7.87 6.35 2.54 BSC
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf
notes: () Complies with JEDEC Standard MS00. (2) All dimensions are in millimeters. (3) Dimensioning and tolerancing per ANSI Y4.5M-982
Doc. No. 04, Rev. D
0
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C256
8-lEAD 150 MIl WIDE SOIC (W)
E E
D A 1 e b A
h x 45 C
L
SyMbOl A A b C D E E e h L 1
MIn 0.0 .35 0.33 0.9 4.80 5.80 3.80
nOM
MAX 0.25 .75 0.5 0.25 5.00 6.20 4.00
.27 BSC 0.25 0.40 0 0.50 .27 8
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf
notes: (1) Complies with JEDEC specification MS-012 dimensions. (2) All linear dimensions are in millimeters.
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Doc No. 04, Rev. D
CAT24C256
8-lEAD 208 MIl WIDE SOIC, EIAJ (X)
E
b D A e A1
c
1
L
SYMBOL A1 A b c D E E1 e L 1
MIN 0.05 0.36 0.19 5.13 7.75 5.13
NOM
MAX 0.25 2.03 0.48 0.25 5.33 8.26 5.38
1.27 BSC 0.51 0 0.76 8
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf
notes: (1) Complies with EIAJ specification. (2) All linear dimensions are in millimeters.
Doc. No. 04, Rev. D
2
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C256
ORDERIng InfORMATIOn
Prefix CAT Device # 24C256 W Suffix I -- G T3
Company ID
Product Number
Temperature Range I = Industrial (-40C to +85C)
Tape & Reel T: Tape & Reel 2: 2000/Reel(4) 3: 3000/Reel
Package L: PDIP W: SOIC, JEDEC X: SOIC, EIAJ(4)
Notes: () All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu.
Lead Finish Blank: Matte-Tin G: NiPdAu
(3) The device used in the above example is a CAT24C256WI-GT3 (SOIC-JEDEC, Industrial Temperature, NiPdAu, Tape & Reel). (4) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT24C256XI-T2. (5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
(c) 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
3
Doc No. 04, Rev. D
REVISIOn HISTORy
Date 0/07/05 /6/05 02/02/06 Revision Comments A B C Initial Issue Update Ordering Information Add Tape and Reel Specifications Update Ordering Information Update Package Outlines. Add SOIC, EIAJ Package Outlines Update A.C. Characteristics. Add A.C. Test Conditions 0/2/07 D Update Figures , 3 and 4 Delete Package Marking. Deleted Tape and Reel Updated Ordering Information
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Publication #: Revison: Issue date:
04 D 0/2/07

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